Interconnect structures

ABSTRACT

Representative techniques and devices, including process steps may be employed to mitigate undesired dishing in conductive interconnect structures and erosion of dielectric bonding surfaces. For example, an embedded layer may be added to the dished or eroded surface to eliminate unwanted dishing or voids and to form a planar bonding surface. Additional techniques and devices, including process steps may be employed to form desired openings in conductive interconnect structures, where the openings can have a predetermined or desired volume relative to the volume of conductive material of the interconnect structures. Each of these techniques, devices, and processes can provide for the use of larger diameter, larger volume, or mixed-sized conductive interconnect structures at the bonding surface of bonded dies and wafers.

PRIORITY CLAIM AND CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit under 35 U.S.C. § 119(e)(1) of U.S.Provisional Application No. 62/748,653, filed Oct. 22, 2018, and of U.S.Provisional Application No. 62/902,207, filed Sep. 18, 2019, which areboth hereby incorporated by reference in their entirety.

FIELD

The following description relates to integrated circuits (“ICs”). Moreparticularly, the following description relates to manufacturing IC diesand wafers.

BACKGROUND

Microelectronic elements often comprise a thin slab of a semiconductormaterial, such as silicon or gallium arsenide, commonly called asemiconductor wafer. A wafer can be formed to include multipleintegrated chips or dies on a surface of the wafer and/or partlyembedded within the wafer. Dies that are separated from a wafer arecommonly provided as individual, prepackaged units. In some packagedesigns, the die is mounted to a substrate or a chip carrier, which isin turn mounted on a circuit panel, such as a printed circuit board(PCB). For example, many dies are provided in packages suitable forsurface mounting.

Packaged semiconductor dies can also be provided in “stacked”arrangements, wherein one package is provided, for example, on a circuitboard or other carrier, and another package is mounted on top of thefirst package. These arrangements can allow a number of different diesor devices to be mounted within a single footprint on a circuit boardand can further facilitate high-speed operation by providing a shortinterconnection between the packages. Often, this interconnect distancecan be only slightly larger than the thickness of the die itself. Forinterconnection to be achieved within a stack of die packages,interconnection structures for mechanical and electrical connection maybe provided on both sides (e.g., faces) of each die package (except forthe topmost package).

Additionally, dies or wafers may be stacked in a three-dimensionalarrangement as part of various microelectronic packaging schemes. Thiscan include stacking a layer of one or more dies, devices, and/or waferson a larger base die, device, wafer, substrate, or the like, stackingmultiple dies or wafers in a vertical or horizontal arrangement, andvarious combinations of both.

Dies or wafers may be bonded in a stacked arrangement using variousbonding techniques, including direct dielectric bonding, non-adhesivetechniques, such as ZiBond® or a hybrid bonding technique, such as DBI®,both available from Invensas Bonding Technologies, Inc. (formerlyZiptronix, Inc.), an Xperi company. The bonding includes a spontaneousprocess that takes place at ambient conditions when two preparedsurfaces are brought together (see for example, U.S. Pat. Nos. 6,864,585and 7,485,968, which are incorporated herein in their entirety).

When bonding stacked dies using a direct bonding technique, it isusually desirable that the surfaces of the dies to be bonded beextremely flat and smooth. For instance, in general, the surfaces shouldhave a very low variance in surface topography (i.e., nanometer scalevariance), so that the surfaces can be closely mated to form a lastingbond. One or more bonding surfaces of the dies or wafers is usuallyplanarized, using chemical-mechanical polishing (CMP), or the like, toachieve the extremely flat and smooth surface(s) desired for bonding.

Respective mating surfaces of the dies or wafers to be bonded (which maycomprise silicon, or another suitable material) often include conductiveinterconnect structures (which may be metal) embedded within aninorganic dielectric layer (e.g., such as an oxide, nitride, oxynitride,oxycarbide, carbides, nitrocarbides, diamond, diamond like materials,glasses, ceramics, glass-ceramics, and the like) at the bonding surface.

The conductive interconnect structures may be formed by damascenetechniques (for example), and may include structures having varyingwidths and sizes. The conductive interconnect structures can be arrangedand aligned at the bonding surface so that conductive interconnectstructures from the respective die surfaces are joined during thebonding. The joined interconnect structures form continuous conductiveinterconnects (for signals, power, heat transmission, mechanicalstability, etc.) between the stacked dies or wafers.

The exposed surfaces of embedded conductive interconnect structures mayalso be planarized, separately or together with the bonding surfaces ofthe dies or wafers. The profile and/or topography of the exposedsurfaces of the conductive interconnect structures can be important toforming reliable continuous conductive interconnects between the dies orwafers, as well as important to forming reliabledielectric-to-dielectric bonds between the dies or wafers.

BRIEF DESCRIPTION OF THE DRAWINGS

The detailed description is set forth with reference to the accompanyingfigures. In the figures, the left-most digit(s) of a reference numberidentifies the figure in which the reference number first appears. Theuse of the same reference numbers in different figures indicates similaror identical items.

For this discussion, the devices and systems illustrated in the figuresare shown as having a multiplicity of components. Variousimplementations of devices and/or systems, as described herein, mayinclude fewer components and remain within the scope of the disclosure.Alternatively, other implementations of devices and/or systems mayinclude additional components, or various combinations of the describedcomponents, and remain within the scope of the disclosure.

FIGS. 1A-1D show cross-sections of an example substrate having embeddedconductive interconnect structures.

FIG. 2 shows a prior art solution to dishing of conductive interconnectstructures.

FIGS. 3A-3G show cross-sections of an example substrate having embeddedconductive interconnect structures, including an example technique formitigating undesired dishing of the conductive interconnect structures,according to an embodiment.

FIGS. 4A-4C show cross-sections of an example substrate having embeddedconductive interconnect structures, including an example technique formitigating undesired dishing of the conductive interconnect structuresand erosion of the substrate, according to an embodiment.

FIGS. 5A-5D show cross-sections of an example substrate having embeddedconductive interconnect structures, including another example techniquefor mitigating undesired dishing of the conductive interconnectstructures and erosion of the substrate, according to an embodiment.

FIG. 6 shows an example top layer process technique for forming abonding layer on a substrate with embedded conductive interconnectstructures, according to an embodiment.

FIGS. 7A-7D show cross-sections of an example substrate having embeddedconductive interconnect structures, including an example technique forforming openings in the conductive interconnect structures, according toan embodiment.

FIGS. 8A-8D show cross-sections of an example substrate having embeddedconductive interconnect structures, including another example techniquefor forming openings in the conductive interconnect structures,according to an embodiment.

FIGS. 9A-9C show cross-sections of example substrates having embeddedconductive interconnect structures with openings, including bondingsolutions using the substrates, according to various embodiments.

FIGS. 10A-10D show cross-sections of example substrates having embeddedconductive interconnect structures with openings, including additionalbonding solutions using the substrates, according to variousembodiments.

FIGS. 11A-11D show cross-sections of example substrates having embeddedconductive interconnect structures with openings, including anotherexample technique for forming the openings, and bonding solutions usingthe substrates, according to various embodiments.

FIG. 12 shows a cross-section of a substrate having embedded conductiveinterconnect structures with openings, utilized as an optical device,according to an embodiment.

FIG. 13 is a text flow diagram illustrating an example process offorming a substrate having embedded conductive interconnect structureswith openings, according to an embodiment.

DETAILED DESCRIPTION Overview

Representative techniques and devices, including process steps may beemployed to mitigate undesired dishing in conductive interconnectstructures and erosion of dielectric bonding surfaces. For example, anembedded layer may be added to the dished or eroded surface to eliminateunwanted dishing or voids and to form a planar bonding surface.Additional techniques and devices, including process steps may beemployed to form desired openings in conductive interconnect structures,where the openings can have a predetermined or desired volume relativeto the volume of conductive material of the interconnect structures.Each of these techniques, devices, and processes can provide for the useof larger diameter, larger volume, or mixed-sized conductiveinterconnect structures at the bonding surface of bonded dies andwafers.

In some embodiments, one or more protective layers may also be depositedwithin unintentional or intentionally recessed portions of conductiveinterconnect structures to prevent or eliminate atom migration (e.g., tosuppress surface mobility) within the recessed portions. Protectivelayers may include conductive or nonconductive materials in variousembodiments.

Various implementations and arrangements are discussed with reference toelectrical and electronics components and varied carriers. Whilespecific components (i.e., dies, wafers, integrated circuit (IC) chipdies, substrates, etc.) are mentioned, this is not intended to belimiting, and is for ease of discussion and illustrative convenience.The techniques and devices discussed with reference to a wafer, die,substrate, or the like, are applicable to any type or number ofelectrical components, circuits (e.g., integrated circuits (IC), mixedcircuits, ASICS, memory devices, processors, etc.), groups ofcomponents, packaged components, structures (e.g., wafers, panels,boards, PCBs, etc.), and the like, that may be coupled to interface witheach other, with external circuits, systems, carriers, and the like.Each of these different components, circuits, groups, packages,structures, and the like, can be generically referred to as a“microelectronic component.” For simplicity, unless otherwise specified,components being bonded to another component will be referred to hereinas a “die.”

Referring to FIGS. 1A and 1B, in some examples a damascene technique, orthe like, may be used to form embedded conductive structures in theinsulating layer 102 of a die or wafer. A barrier layer 106 may bedeposited over one or more cavities 104 within the insulating layer 102,followed by a seed layer 108. The cavities 104 may be of different sizes(i.e., volumes and widths), having different areas and located withvarious spacing relative to each other, as desired and/or by design.

As shown at FIG. 1B, the cavities 104 can be filled using anelectroplating bath or other technique with a conductive material 110such as copper, for example. The conductive material 110 may comprisethe same material as the seed layer 108, or a different material in somecases. Extra conductive material 110 plating is removed from the bondingsurface 112 as shown in FIG. 1C. Conductive material 110 remainingwithin the damascene cavities 104 forms conductive interconnectstructures 114.

Referring to FIG. 1C, preparing a bonding surface 112 of a die or waferfor direct bonding can include planarizing the exposed surfaces ofembedded conductive interconnect structures 114 along with theinsulating (e.g., dielectric, etc.) layer 102 of the die or wafer. Thiscan provide the desired profile and topography of the exposed surfacesof the conductive interconnect structures 114 and the top insulatinglayer 102. As a result of a discontinuity in the properties (differencein mechanical properties, polishing rates, etc.) of the conductivematerial 110 (e.g., metal, for example copper) of the interconnectstructures 114 and the insulator material 102 (e.g., silicon dioxide,etc.) of the die or wafer surface, and their respective interactionswith the polishing pad, polishing slurry, and other process parameters,the planarizing can produce dielectric erosion (see, for example erosion404 at FIG. 4A) in high metal pattern density areas and dishing 116 inthe exposed surface of the interconnect structures 114.

In general, the higher the metal pattern density, the greater theerosion. Similarly, the larger the area of the exposed surface of theconductive interconnects 114, the deeper the dishing defect 116. Bothresult in a notable variance in the overall surface topography of thedie or wafer. The variance may be enough to weaken a direct bond orreduce the reliability of the bond at the locations of the surfacevariance (including reducing the reliability of metal to metal bonds).

While some recessing may be desirable, as discussed further below, aconsequence of undesirable dishing on the exposed surface of conductiveinterconnect structures 114 can include the need for higher thandesirable temperatures to bond the prepared devices 118. This can limitthe types of devices that can be bonded or limit the size of theinterconnects 114 used. Further, some interconnect structures 114 withlarge surface areas can experience dishing 116 that may be too deep toform a reliable diffusion bond. For instance, the metal of the structure114 may not expand enough at annealing temperatures to form the bond. Ifa bond is formed, it may be defective and unreliable.

For example, in some cases as shown at FIG. 1D, the excessive dishing116 of structures 114 with larger surface areas can result in a void 120within the bonded structures 114, including after annealing or postbonding higher temperature thermal treatment step. The voids 120 cancontribute to reliability concerns, since they can allow the migrationof voids or vacancy dislocation defects emitted from the voids 120 dueto surface mobility in metals atoms (such as copper, for example)causing device failures, as well as limiting the current carryingcapacity of the interconnect structures 114.

An example of an attempt at mitigating the effects of excessive dishing116 is shown by the process 200 at FIG. 2. For instance, a device 118having conductive interconnect structures 114 with excessive dishing 116is shown at block A. At block B, the process includes adding aninsulating layer 202, such as a dielectric layer for example, over theuneven bonding surface 112, and then resurfacing the added bonding layer202 (via CMP planarization or the like) at block C.

As shown at block D, interconnect structures 204 with smaller widths(L2) and smaller exposed surface areas than the larger widths (L1) andlarger surface areas of the interconnect structures 114 can be formed(using single or dual damascene processes, for instance) in the addedlayer 202. The new interconnect structures 204 extend through the addedbonding layer 202 and make electrical contact with the dished conductivestructures 114 below. The goal is to reduce the exposed metal area onthe new bonding layer 202 to reduce surface variance for a more reliabledirect bond with stacked substrates 206 (see block E). However, theprocess of adding an additional bonding layer 202 can add 10 or moremanufacturing steps, greatly increasing the cost of the devices 118produced. Further, the new interconnect structures 204 (for example witha width L2) tend to be much smaller in area than the original structures114 (for example with a width L1) below, often negatively affectingelectrical connection properties and limiting wiring design freedom.

Example Implementations

In various implementations, innovative techniques and devices are usedto mitigate the effects of dishing and recesses 116 in the surface ofinterconnect structures 114 of various sizes (including large areastructures, for instance having a width or diameter of 10 microns ormore), to form reliable low temperature metallic bonds. The techniquesand devices are effective to prepare a direct bonding surface 112 ondies and wafers having embedded conductive interconnect structures 114with varying widths (e.g., diameters), dimensions, and sizes, includingmixed sizes on a single die surface 112, for instance structures havinga width or diameter of 1 micron to over 1000 microns. Further, thetechniques and devices allow the use of a standard manufacturingtechnique for surface 112 preparation on such varied dies and wafers. Inthe implementations, an embedded layer 304 (see FIG. 3D) is added to thedished surface of the interconnect structures 114 to reduce or eliminaterecessing and/or voids. In an embodiment, the embedded layer 304 may becomprised of a dielectric material, such as SiC, SiC/SiO₂, SiN/SiO₂, orthe like. For example, the embedded layer 304 may be comprised of thesame or a different dielectric as the die or wafer surface 102. In otherembodiments, the embedded layer 304 may be comprised of a conductivematerial, such as tungsten, an alloy of tungsten, a nickel alloy, or thelike. Alternatively, the embedded layer 304 may include a low CTEmaterial, a silicon containing material, such as doped or undopedpolysilicon (which may form a silicide), or other suitable material.Still further, multiple coats or layers of insulating and/or conductivematerials may be used.

Referring to FIGS. 3A and 3B (showing cross-sectional profile views),patterned metal and oxide layers are frequently provided on a die,wafer, or other microelectronic substrate (hereinafter “die 302”) as ahybrid bonding, or DBI®, surface layer. A representative device die 302may be formed using various techniques, to include a base substrate (seeFIG. 6) and one or more insulating or dielectric layers 102. The basesubstrate may be comprised of silicon, germanium, glass, quartz, adielectric surface, direct or indirect gap semiconductor materials orlayers or another suitable material. The insulating layers 102 aredeposited or formed over the base, and may be comprised of inorganicdielectric material layers such as an oxide, nitride, oxynitride,oxycarbide, carbides, carbonitrides, diamond, diamond like materials,glasses, ceramics, glass-ceramics, and the like.

As discussed above, in some examples a damascene technique, or the like,may be used to form embedded conductive structures 114 in the insulatinglayer 102 of the die or wafer. A barrier layer 106 may be deposited overone or more cavities 104 within the insulating layer 102, followed by aseed layer 108, prior to depositing the material of the conductiveinterconnect structures 114, such that the barrier layer 106 is disposedbetween the conductive interconnect structures 114 and the insulatinglayer 102. The cavities 104 may be of different sizes (i.e., volumes andwidths), having different areas and located with various spacingrelative to each other, as desired and/or by design. A barrier layer 106may be comprised of tantalum or titanium or cobalt containing materials,for example, or other conductive materials, to prevent or reducediffusion of the material of the conductive interconnect structures 114into the insulating layer 102.

As shown at FIG. 3B, the cavities 104 can be filled using anelectroplating bath or other technique with a conductive material 110such as copper or a copper alloy, for example. The conductive material110 may comprise the same material as the seed layer 108, or a differentmaterial in some cases. Extra conductive material 110 plating is removedfrom the bonding surface 112 as shown in FIG. 3C. Conductive material110 remaining within the damascene cavities 104 forms conductiveinterconnect structures 114.

Forming a bonding surface 112 includes finishing the surface 112 of theinsulating layer 102 to meet dielectric roughness specifications and anymetallic layers (e.g., copper traces, structures, pads, etc.) to meetrecess specifications, to prepare the surface 112 for direct bonding. Inother words, the bonding surface 112 is formed to be as flat and smoothas possible, with very minimal surface topography variance.

Referring to FIG. 3C, preparing the bonding surface 112 of the die 302or wafer for direct bonding can include planarizing the exposed surfacesof embedded conductive interconnect structures 114 along with theinsulating (e.g., dielectric, etc.) layer 102 of the die 302 or wafer.This can provide the desired profile and topography of the exposedsurfaces of the conductive interconnect structures 114 and the topinsulating layer 102. Various conventional processes, such as chemicalmechanical polishing (CMP) may be used to achieve the low surfaceroughness. This process provides the flat, smooth surface 112 that canresult in a reliable bond.

However, as discussed above, a result of a discontinuity in theproperties (difference in mechanical properties, polishing rates, etc.)of the conductive material 110 (e.g., metal, for example copper,aluminum, etc.) of the interconnect structures 114 and the insulatormaterial 102 (e.g., silicon dioxide, etc.) of the die or wafer surface,and their respective interactions with the polishing pad, polishingslurry, and other process parameters, the planarizing can producedielectric erosion 402 (see FIG. 4A) in the dielectric portions adjacentto the interconnect structures 114 and dishing 116 in the exposedsurface of the larger interconnect structures 114.

In various implementations, as shown at FIG. 3D, the embedded layer 304is formed (e.g., deposited, coated, etc.) over the previously preparedsurface 112 of the die 302, including the surfaces of the embeddedstructures 114 having recesses 116. The embedded layer 304 is planarizedwith a hard CMP pad. As shown at FIG. 3E, the embedded layer 304 may beplanarized to the point of revealing the highest surfaces of theembedded interconnect structures 114, which now include the embeddedlayer 304 within a perimeter of the exposed portion of the structures114, partially or fully filling the undesirable recesses 116 andcovering a surface of the recesses 116. The prepared bonding surface306, which includes the conductive interconnect structures 114 and theembedded layer 304 as well as the planarized insulating layer 102, nowhas minimal surface topography variance, and can be reliably bonded tothe bonding surface of another die 302, wafer, etc. using direct bondingtechniques.

For instance, as shown at FIGS. 3F and 3G, a like die 302 (or wafer,etc.) that may have a similarly prepared bonding surface can be bondedto the bonding surface 306 to form a bonded device 312. In anembodiment, the joined conductive interconnect structures 114 can bediffusion bonded at lower temperatures, forming a unified conductivestructure 310, and can include the embedded layer 304 within the unifiedconductive structure 310. This makes possible the use of conductiveinterconnect structures 114A with larger width or surface area,mixed-size conductive interconnect structures 114, and denser spacing ofconductive interconnect structures 114B and 114C on the bonding surface306.

In some cases, as shown at FIG. 3G, where the embedded layer 304comprises an insulating material, the embedded layer 304 fills the void120 that would be present otherwise, effectively suppressing the surfacemobility of the atoms of the metal layer at the joint region orinterface between the embedded layer 304 and the conductive interconnectstructure 114. The embedded layer 304 is located within the perimeter,thus allowing the outer perimeter of the bonded conductive structures114 to diffusion bond and to function electrically. In some instances,the outer perimeter is maintained to have a predetermined thickness (orwidth) for desired conductivity. Further, the material of the embeddedlayer 304 may be chosen for high bonding capability (e.g., SiC,SiC/SiO₂, SiN/SiO₂, or the like).

In other cases, where the embedded layer 304 comprises a conductivematerial, the embedded layer 304 has the previously discussed qualities(e.g., suppressing surface mobility within the recess, forming adesirable bonding surface with low surface topography variance, etc.),and also assists in conducting the signal, power, etc. at the unifiedconductive structure 310. The conductive material (e.g., tungsten, analloy of tungsten, a nickel alloy, or the like) of the embedded layer304 may be selected to have predetermined low surface mobilitytendencies, reducing or avoiding atom migration. In some cases it may bepreferable for the melting point of the embedded layer 304 to be higherthan that of the material 110 of the conductive interconnect structure114. In some cases, the embedded layer 304 may be comprised of multiplemetals or like materials.

The embedded layer 304 disclosed herein is distinguished from thesealing layer, as described in U.S. Pat. No. 8,809,123 to Liu et al.,which has properties such that when the sealing layer (such asgermanium, tin, or the like) is combined with the material of theconductive pads (e.g., copper) and heated to a predeterminedtemperature, a metal in a eutectic phase is formed. In contrast, theembedded layer 304 of the instant disclosure lines or coats the portion(e.g., the recess 116) of the exposed surface of the conductiveinterconnect structure 114, reducing the gap of the recess 116 to form amore flat bonding surface and covering the exposed metal of theinterconnect structure 114 to suppress atom migration at the recess 116.

Referring to FIG. 3G, in an alternate embodiment, where the area of aninterconnect 114 surface is particularly large, for instance having awidth or diameter of 100 microns or more for example, the embedded layer304 may also experience some dishing during planarization. In theembodiment, the dishing may result in a void 308 (or air gap) in theembedded layer 304 within the unified conductive structure 310. However,the void 308 in the embedded layer 304 may be inconsequential, since theembedded layer 304 still covers the metal of the interconnect structures114, reducing surface mobility of the material 110 of the conductiveinterconnect structures 114. In one embodiment, a width of the occludedvoid 308 or cavity within the embedded layer 304 is less than 50% of awidth of the interconnect structure 114.

In various implementations, the thickness of the embedded layer 304 isgreater than a thickness of the barrier layer 106 deposited during thedamascene process. For instance, the embedded layer 304 may have athickness of about 15 to 30 nanometers over the surface of the recess116. In other implementations, the embedded layer 304 may be thickerthan 30 nanometers for some recesses 116. For instance, the depth of therecess 116 may be about 1 to 5 microns, in some examples. In someimplementations, the thickness of the embedded layer 304 is less than awidth (or diameter) of the recess 116.

In various embodiments, a width (or diameter) of the surface area of theembedded layer 304 is less than a width (or diameter) of the otherwiseexposed surface of the conductive interconnect structure 114. Forinstance, a width or diameter of the embedded layer 304 may be less than50%, 20%, 10%, 5%, or 2% of a width or diameter of the surface of theconductive interconnect structure 114, in various examples.

In some embodiments, the spacing of the interconnect structures 114 maybe reduced for greater wiring design freedom. For example, previousratios of pad pitch to pad width (or diameter) have been kept larger, onthe order of 2:1 and 3:1 for some larger pads, due to increasedinterconnect 114 dishing and dielectric 102 erosion with closer ratios.In the embodiments, the pitch of the interconnect 114 pads may bereduced to less than 2. In this embodiment, a distance between twoadjacent interconnect pads 114 is less than a width of the interconnect114 pad when using the disclosed techniques and devices. For oneexample, a set of adjacent 20 micron interconnect 114 pads may now havea pitch of about 25 microns when applying the disclosed techniques anddevices.

Referring to FIGS. 4A-4C, in another implementation, the embedded layer304 may also be used outside of the recess 116 of the conductivestructure 114, including inside or outside the barrier layer 106 of theconductive structure 114. In one example, as shown at FIG. 4A, theconductive structure 114 may have one or more cavities 402 of missingmetal at the perimeter of the structure 114. For instance, processingsteps may cause some of the conductive structure 114 to corrode off, orthe like, leaving the cavities 402 behind.

In an embodiment, as shown at FIG. 4B, the deposited embedded layer 304can fill the cavities 402 where the metal of the structure 114 ismissing. As shown at FIG. 4C, the embedded layer 304 filling thecavities 402 can smooth out the surface of the bonding layer 306 whenthe embedded layer 304 is planarized. In some embodiments, polishing theembedded layer 304 traps the material of the embedded layer 304 in thecavities 402 between the barrier layer 106 and the conductive structure114.

In another example (as also shown at FIGS. 4A-4C), the dielectricmaterial 102 at the surface adjacent to the conductive structure 114 maybe eroded (or “rounded,” see 404) at the outer edges of the conductivestructure 114 or at the barrier layer 106 during the planarization step.The erosion 404 may be more pronounced at regions with high metaldensity, for instance. As shown at FIG. 4A, the dielectric erosion 404can comprise one or more cavities or recesses in the dielectric 102outside the edges of the conductive structure 114 or the barrier layer106. As shown at FIG. 4B, the deposited embedded layer 304 can also fillthe cavities 404 where the dielectric 102 is missing. As shown at FIG.4C, the embedded layer 304 filling the cavities 404 can smooth out thesurface 306 of the bonding layer 102 when the embedded layer 304 isplanarized. In some embodiments, polishing the embedded layer 304 trapsthe material of the embedded layer 304 in the cavities 404 or recesses.While the cavities 402 and 404 may be inadvertently formed as part ofthe process, such cavities or recesses may be provided intentionally atthese locations or elsewhere on the bonding surface and may have anysuitable shape, profile, or configuration as desired or required.

In a further embodiment, referring to FIG. 5A, another technique may beemployed to mitigate the effects of missing metal portions of theconductive interconnect structures 114, or the like, while remedying thedishing 116 of the structures 114. In the embodiment, selective portions502 of the dielectric layer 102 may be removed such that portions ofsidewalls 504 of the conductive interconnect structures 114 protrudeabove the surface of the dielectric layer 102 (FIG. 5B).

As shown at FIG. 5C, the embedded layer 304 may be deposited over thesurface of the insulating layer 102, including the interconnectstructures 114. The embedded layer 304 can build up the surface of theinsulating layer 102, providing a new layer 506 to be prepared forbonding. The embedded layer 304 may now contact at least a portion ofthe metal sidewall 504 of the interconnect structures 114 and/or thebarrier layer 106. As shown at FIG. 5D, the embedded layer 304 can beplanarized to the point of revealing the highest points of theinterconnect structures 114, while retaining a flat surface with minimalsurface topography variance. The interconnect structures 114 may nowinclude the embedded layer 304 within a perimeter of the exposed portionof the structures 114 (filling the recesses 116). Any other cavities(e.g., 402, 404) in the interconnect structures 114 and/or theinsulating layer 102 are also covered by the embedded layer 304.

Referring to FIG. 6, in various implementations, the disclosed techniquecan also be performed (shown as process 600) to provide a passivationlayer 606 over the insulating layer 102, as a functional layer, aprotective layer, or a preferred bonding layer. Block A shows a cavity602 in an insulating layer 102, over a base layer 604, that is filledwith a conductive material 110 (e.g., copper, etc.) using a damascenetechnique, or the like (as discussed above). As shown at block B, theconductive material over-fill from the damascene process is removed, byplanarization, etch, or the like, forming the conductive interconnectstructure 114 in the cavity 602. In some cases, it may be advantageousto make the surface of the insulating layer 102 as flat and smooth (asif for direct bonding, for instance) as possible.

At block C, portions 502 of the dielectric 102 can be selectivelyremoved as desired (e.g., about 30-100 nm), using a selective wet etchfor example, leaving the conductive structure 114 protruding from theinsulating layer 102. At block D, the embedded layer 304 is depositedover the surface of the insulating layer 102, including the interconnectstructures 114. The embedded layer 304 may contact at least a portion ofthe metal sidewall 504 of the interconnect structures 114 and/or thebarrier layer 106. The embedded layer 304 can be planarized (CMP, forexample) to the point of revealing the highest point(s) of theinterconnect structures 114, while retaining a flat surface with minimalsurface topography variance, as discussed above and shown at block E.The passivation layer 606, which may comprise a preferred bonding layer,a protective layer, and/or a functional layer for the die 302 comprisesthe planarized embedded layer 304 remaining on the insulating layer 102.

Additional Embodiments

In general, when directly bonding dies or wafers having bonding surfacescontaining a combination of a dielectric layer 102 and one or more metalfeatures, such as the embedded conductive interconnect structures 114,the dielectric surfaces 102 bond first and the metal 110 of the features114 expands afterwards, as the metal 110 is heated during annealing. Theexpansion of the metal 110 can cause the metal 110 from both dies 302 tojoin into a unified conductive structure 310 (metal-to-metal bond).While both the insulating layer 102 and the metal 110 are heated duringannealing, the coefficient of thermal expansion (CTE) of the metal 110relative to the CTE of the insulating layer 102 generally dictates thatthe metal 110 expands much more than the insulating layer 102 at aparticular temperature (e.g., ˜300 C). For instance, the CTE of copperis 16.7, while the CTE of fused silica is 0.55, and the CTE of silicon(e.g., base 604) is 2.56. In some cases, the greater expansion of themetal 110 relative to the insulating layer 102 can be problematic fordirect bonding stacked dies 302.

Some embedded conductive interconnect structures 114 may extendpartially into the insulating layer 102 below the prepared bondingsurface 112. For instance, some patterned metal features may be about0.5-3 microns thick. Other conductive interconnect structures 114 maycomprise thicker (e.g., deeper) structures, including metal throughsilicon vias (TSVs) or the like, that may extend partly or fully throughthe insulating layer 102 and include a larger volume of metal 110. Forinstance, a TSV may extend about 100 microns or more, depending on thethickness of the substrate. In some applications, it may be desirable toform large diameter metal structures 114, for instance having a width ordiameter of 10 microns to over 100 microns, which would also include alarger volume of metal 110. As mentioned above, the metal 110 of thesestructures 114 expands when heated. In some cases, the metal 110expansion can cause undesirable localized stress, including potentialdelamination of the bonding surfaces at the location of the structures114. In a worst-case, the stress of the expanded metal 110 may separatethe bonded dielectric surfaces 112 of the stacked dies 302.

Also, it can be relatively expensive to form fully-filled large cavities104 with metal or other conductive material 110. For example, fillingTSV arrays having a diameter of 5 microns and a depth of 100 microns byelectroplating methods may require 10 to 20 minutes of metal platingtime. However, filling TSV arrays having a diameter of 20 microns and asimilar depth may require plating times between 120 to 400 minutes oreven longer. The longer plating times reduces the throughput of theplating tool for filling larger cavities 104. Similarly, it can costmore to planarize the larger metal filled cavities 104 to removeunwanted metal on the bonding surface. In practice, the larger the metalfilled cavity 104 the greater the mismatch stress due to differences inthe coefficient of thermal expansion (CTE) between the coated metal 110and the insulating layer 102. In the case of large metal TSVs, thelarger the diameter of the via, the larger the keep out zone for devicesin the device portion of the substrate.

Referring to FIGS. 7A-7D, in various embodiments, devices, techniques,and processes may be employed to mitigate the effects of undesirablehigh-stress, including the potential for delamination due to metal 110expansion, improve throughput, and reduce cost of ownership for formingplanar metal in large cavities 104. This can allow for the use of largerdiameter structures 114, larger volume structures 114, or mixed-sizedstructures 114. As an example, the diameter of 114A is larger than thediameter of 114B, which is in turn larger than that of 114C.

For example, in various embodiments, an opening 702 may be intentionallyformed in a conductive interconnect structure 114. The opening 702 mayextend a predetermined depth below the surface of the conductiveinterconnect 114. For a given metal coating time, the volume of openingof 702A can be larger than that of 702B and the volume of opening 702Bcan be larger than 702C. The volume of the opening 702 may be selectedbased on the material 110 of the conductive interconnect 114, itsthickness or volume of material 110, and its anticipated expansionduring annealing. In various embodiments the opening 702 may include anyrecessed portion, gap, cavity, hollow, or the like in the conductiveinterconnect structure 114 that provides room for the material 110 ofthe interconnect structure 114 to expand into. A suitably sized opening702 can reduce or eliminate the stress of the expanding material 110 onthe bond joint 306 of the stacked dies 302 or wafers, since the metal110 can expand into the opening 702. The width of the opening 702 mayrange for example between less than 100 nm to over 20 microns. With anopening 702 of predetermined size, it can still allow the material 110of respective interconnect structures 114 to reliably join and formcontinuous conductive interconnects 310 between the stacked dies 302 orwafers.

In various embodiments, the opening 702 may be intentionally formed tohave a desired preselected volume (e.g., to accommodate excessivestresses resulting from the mismatch in the thermal expansion of thecoated metal 110 in the cavity 104 and the surrounding insulator 102materials). In other embodiments, the opening 702 may be allowed to formas part of processing the bonding surface 306 of the die 302 or wafer.In such cases, the volume of the opening 702 may be predictable based onthe processes and materials involved.

For example, in some embodiments, the opening 702 may be formedintentionally while the conductive interconnect structure 114 is formed.For instance, as shown at FIGS. 7A-7C, conductive interconnectstructures 114 may be formed using damascene techniques, and may includecavities 104 and structures 114 having mixed widths (104A, 104B, and104C) and depths. As illustrated at FIG. 7A, one or more damascenecavities 104 may be formed in the surface of the dielectric layer 102 ofthe die 302 or wafer or substrate of interest, to extend partially orfully through the dielectric layer 102. In one example, a cavity 104 mayhave a width or diameter of at least 10 microns and a depth of at least5 microns or even 10 microns. Alternately, the cavities 104 may beformed to extend into the base substrate (not shown—see base 604 at FIG.6 for example) of the die 302 or wafer. A barrier layer 106 and a seedlayer 108 are deposited over the exposed surfaces of the cavities 104.

As shown at FIG. 7B, the cavities 104 are partially filled withconductive material 110 (e.g., copper, a copper alloy, etc.) using asuper-filling electroplating bath, or using a conformal electroplatingor electroless plating bath or the like. In some embodiments, theconductive layer 110 may be coated into the cavity 104 by a physicalvapor deposition method (PVD) or by an atomic layer deposition method,chemical vapor deposition method, or spin coating of the conductivelayer 110 into the cavity 104. The partial filling of the conductivelayer 110 in the cavities 104 results in conductive interconnectstructures 114 with intentional openings 702 (e.g., 702A, 702B, and702C) within the damascene cavities 104 (e.g., 104A, 104B, and 104C,respectively).

The bonding surface 306 of the die 302 or wafer or substrate of interestis planarized (using chemical-mechanical polishing (CMP), or the like)to prepare the dielectric surface 102 and conductive interconnectstructures 114 for bonding. This includes removing the unwanted layer ofplating 110 and other conducting barrier layer 106 from the damasceneprocess from the dielectric bonding surface 306, as illustrated in FIG.7C. The remaining openings 702′ (e.g., 702A′, 702B′ and 702C′) areconfined to the interconnect structures 114, and may have predeterminedvolumes. In one embodiment, a width (“w”) of the remaining opening 702′at the bonding surface 306 of the die 302 or wafer is greater than athickness of the barrier layer 106 between the conductive layer 110 andthe dielectric layer 102. Also, the width of the remaining opening 702A′is larger than the width of remaining opening 702B′ and the width ofremaining opening 702B′ is larger than the width of remaining opening702C′. In other applications, a width (“w”) of the remaining opening702′ at the bonding surface 306 is larger than a thickness of theconductive layer 110 within the respective cavity 104. In someapplications, the depth (“d”) of the remaining opening 702′ may be lessthan 50 nm, and preferably less than 100 microns.

The bonding surface 306 of the die 302 or wafer may be ready for bondingto another like die 302 or wafer, or to some other prepared substrate704, to form a bonded device 312. In various embodiments, the substrate704 may comprise the same or a dissimilar or a different material thanthe die 302. For instance, the substrate 704 may comprise a dielectric,a glass, a semiconductor, or other material. After the bondingoperation, in which the planar portion or portions of the conductiveinterconnect structures 114 (114A, 114B and 114C) on the bonding surface306 are directly bonded to the prepared surface of the opposingsubstrate 704, the remaining openings 702′ are occluded within theconductive interconnect structures 114, as depicted in FIG. 7D.

In an alternate process, as shown at FIGS. 8A-8D, after partiallyfilling the damascene cavities 104 with the conductive material 110, aprotective layer 802 may be formed (e.g., deposited, coated, etc.) overthe surface of the conductive material 110, including within the opening702 in the surface of the conductive interconnect structures 114 (seeFIGS. 8C and 8D).

In various embodiments, the protective layer 802 may comprise adielectric material, such as SiO₂, SiC, SiN, SiC/SiO₂, SiN/SiO₂,SiN/polysilicon, inorganic dielectric/organic dielectric or the like.For example, the protective layer 802 may be comprised of the same or adifferent dielectric as the insulating layer 102 of the die 302 or wafersurface. In other embodiments, the protective layer 802 may be comprisedof a conductive material, such as tungsten, an alloy of tungsten, anickel alloy, tantalum or titanium and the various alloys, for exampleTaN/Ta or Ta/TaN, Ti/TiN, cobalt, CoP, NiP, CoWP, CoP/NiP or the like.Still further, the protective layer 802 may include a low CTE material,a silicon containing material, such as doped or undoped polysilicon(which may form a silicide), or other suitable material. Still further,multiple coats or layers of insulating and/or conductive materials maybe used.

The protective layer may be deposited by PVD methods or fromelectrolytic or by electroless plating baths or other techniques.Alternatively, the protective layer 802 may include multiple coats orlayers of insulating and/or conductive materials. In some applications,the protective layer 802 may comprise a conformal coating of one or morematerials. One of the benefits of the protective layer 802 is tosuppress the surface mobility of metal atoms at the surface of theconductive layer 110, adjacent to the protective layer 802 within theopening 702, improving the reliability of the bonded interconnect 114.Thus the protective layer 802 can act as a bonding surface for a portionof the conductive interconnect 114.

In an embodiment, the thickness of the protective layer 802 is less thanthe thickness of the conductive layer 110 within the respective cavities104 bounded with the protective layer 802 and the barrier layer 106. Inother embodiments, the protective layer 802 may be thicker than theconductive layer 110. After planarization of the bonding surface 306,including removing unwanted materials from the bonding surface 306, theremaining openings 702′ (702A′, 702B′ and 702C′) in the surfaces of theinterconnect structures 114 retain the protective layer 802 on theinterior surfaces of the remaining openings 702′, which can havepredetermined volumes.

The die 302 or wafer may be prepared for bonding to another like die 302or wafer (as shown at FIGS. 3F, 3G, 9B, and 9C), and/or to some otherprepared substrate 704 (as shown at FIGS. 7D, 9A, and 9C) to form abonded device 312. In one example, the planarized wafer of FIG. 8D maybe singulated by known methods, the singulated wafer is cleaned andprepared for bonding operation. For instance, the die 302 from thesingulated wafer or wafer may be bonded to a planar substrate 704 orother carrier to form the bonded device 312. In one embodiment, theplanar carrier 704 or the die 302 may include a single or multilevelBEOL interconnect structure 114 or a dielectric comprising one or moreRDL layers. During the bonding operation, the conductive interconnectstructures 114 of the dies 302 are aligned to and mated intimately withthe receiving conductive interconnect structures 114 on the surface ofthe like die 302 or wafer and/or the prepared substrate 704 to form theunified conductive structures 310.

In various cases, as shown at FIGS. 9A-9C, the dies 302 or wafers may bebonded front-to-front (FIG. 9B) or back-to-front (FIG. 9C) and/or bondedto a planar substrate 704 (FIGS. 9A and 9C) to form a bonded device 312.After bonding, the conductive interconnect structures 114 have enclosedcavities 702′ with a protective layer 802 lining the interior surfacesof the cavities 702′. The profile of the occluded cavity 702′ orcavities 702′ viewed from a cross section of the die 302 may begeometrically regular or irregular shapes. In various embodiments, thereceiving substrate 704 may be comprised of a conductive layer occludingone or more cavities 702′, as shown at FIGS. 9A and 9C.

In other words, in an example embodiment, as shown at FIG. 7D, a bondeddevice 312 can comprise a portion of a conductive layer (e.g., part of aconductive interconnect 114 at the bonding surface of the die 302)directly bonded to a substrate 704 and another portion of the conductivelayer (e.g., an interior portion of the occluded cavity 702′ within theconductive interconnect 114) not bonded to the same substrate 704. Andin another implementation, as shown at FIG. 9A, a bonded device 312 cancomprise a portion of conductive layer (e.g., part of a conductiveinterconnect 114 at the bonding surface of the die 302) directly bondedto a substrate 704 and another portion of the conductive layer (e.g., aninterior portion of the occluded cavity 702′ within the conductiveinterconnect 114) directly coated with a protective layer 802 not bondedto the same substrate 704.

In some applications, with wafers or dies 302 comprising TSVs or throughelectrodes, after the bonding operation as shown in FIG. 9B, thebackside of the bonded wafer of dies 302 may thinned and formed toexpose the backside of the conductive structures (TSVs or throughelectrodes). Additional prepared dies 302 or wafers may be electricallycoupled to the exposed TSV on the bonded die 302 or wafer backside. Theelectrically coupling of the said dies 302 or wafer may comprise the useDBI methods or flip chip methods, amongst others.

Further Embodiments

Further embodiments are shown at FIGS. 10A-12. In one embodiment, asshown at FIGS. 10A-10D, the partial-filling of conductive material 110discussed above is applied thinner, and amounts to a conformal ornon-conformal metal coating 1002 within the damascene cavity 104. Thisthinner coating 1002 can result in an opening 702′ with a very largevolume with respect to the conductive interconnect structure 114,depending on the thickness of the conductive layer 1002.

Additionally, as shown at FIG. 10B, the coating 1002 may be thicker insome cases, or have varying thicknesses for different devices 312 orwithin a single device 312. For instance, in some embodiments, thecross-sectional width (“w”) of the opening 702′ is more than 3 timeslarger than the thickness (“t”) of the conductive layer 1002 (on thesidewall of the cavity 104, for example). Also, in some embodiments, adepth (“d”) of the opening 702′ can be greater than a cross-sectionalwidth (“w”) of the opening 702′.

In an implementation, as shown at FIG. 10C, the interior surfaces of theopening 702′ (i.e., the exposed surfaces of the conductive layer 1002)can be coated with the protective coating 802, as described above. Inanother embodiment, as shown at FIG. 10D, a compliant material 1004(such as a fill or encapsulant material, for instance) may be depositedwithin the opening 702′ of a conductive interconnect structure 114 (withor without a protective layer 802). The compliant material 1004 maypartially or totally fill the opening 702.

Referring to FIGS. 11A-12, in some embodiments, the described techniquesand processes can be used to form through-silicon vias 1102 (TSVs), orthe like for devices 312. In the case of a TSV 1102, multiple layers mayline the interior side-walls of the opening 702 within the TSV 1102. Insome embodiments, the TSV 1102 may be formed by a via middle or via lastmethod. Regardless of how the TSV 1102 or thru-substrate via orthru-glass via (TGV) or thru-substrate electrode (TSE) or thru-panel viais formed, a backside reveal process may be applied to expose thepartially conductive interconnect structure 114 from the backside, inthe case of a via middle process.

For example, as shown at FIGS. 11A and 11B, after the partial filling ofthe cavities 104, one or more additional layers 1104 may be applied overthe conductive layer 110, with or without the protective layer 802(depending on the embodiment). In various examples, the one or moreadditional layers 1104 may include one or more dielectric layers, or thelike.

As shown at FIG. 11B, planarizing the bonding surface 306 forms theconductive interconnects 114 having the one or more additional layers1104. Referring to FIG. 11C, the backside of the die 302 may be thinnedand the backside of the conductive interconnects 114 revealed bygrinding, polishing, reactive ion etching methods, and other knownmethods to expose the interior of the conductive interconnect structures114, which forms the TSVs 1102. The TSVs 1102 provide hollows orpass-through conductive openings 702 through the die 302, as shown atFIGS. 11C and 11D. In some embodiments, as shown, the interiorconducting surface of the pass-through opening 702 is lined with adielectric layer 1104. The prepared backside may then be direct bondedto another die 302, wafer, or prepared substrate 704.

As shown at FIG. 11D, one or more components 1106, such as opticaldevices or other microelectronic components may be bonded to the frontside bonding surface 306 of the die 302. In some cases, the TSVs 1102provide electrical or optical signal transmission from the one or morecomponents 1106 to the other die 302, wafer, or prepared substrate 704bonded to the back side of the die 302. For instance, as shown at FIG.12, an optical device 312 is shown. In the example, the substrate 704may comprise one or more layers of glass 1202, and include a reflector1204 and optionally a cavity 1206 as desired for the application. Insuch an instance, the TSVs 1102 may transmit optical signals, and mayalso transmit electrical signals in some cases.

In various other embodiments, other techniques may be used to vary thesurface of a conductive interconnect structure 114, to mitigate theeffects of metal expansion. For instance, in some examples, the surfaceof a conductive interconnect structure 114 may be selectively etched(via acid etching, plasma oxidation, etc.) to provide a desired opening702 depth. In a further embodiment, a conductive interconnect structure114 may be selected, formed, or processed to have an uneven top surface.For example, the top surface of the conductive interconnect structuremay be rounded, domed, convex, concave, irregular, or otherwisenon-flat.

Example Processes

FIGS. 13 and 14 comprise text-based process flows of the above describedprocesses and techniques. Application of the process flows describedprovide for the use of larger width or diameter (e.g., 10 to 1000microns, for example) conductive interconnect structures at the bondingsurface of directly bonded dies, wafers, substrates, and the like.

The order in which the processes are described is not intended to beconstrued as limiting, and any number of the described process blocks inthe processes can be combined in any order to implement the processes,or alternate processes. Additionally, individual blocks may be deletedfrom the processes without departing from the spirit and scope of thesubject matter described herein. Furthermore, the processes can beimplemented in any suitable hardware, software, firmware, or acombination thereof, without departing from the scope of the subjectmatter described herein. In alternate implementations, other techniquesmay be included in the processes in various combinations and remainwithin the scope of the disclosure.

FIG. 13 illustrates a representative process 1300 of mitigatingundesirable recesses (such as recesses 116, for example) in the surfaceof conductive interconnect structures (such as conductive interconnectstructures 114, for example) at the bonding surface of a die (such asdie 302, for example), wafer, or other substrate of interest, accordingto various embodiments. For instance, an embedded layer (such asembedded layer 304, for example) may be formed in the recesses, fillingthe recesses to provide a flat and smooth bonding surface suitable fordirect bonding. The process 1300 refers to FIGS. 1A-6.

In an implementation, at block 1302, the process 1300 includes formingone or more first embedded conductive interconnect structures (such asconductive interconnect structures 114, for example) in a firstsubstrate (such as die 302, for example).

At block 1304, the process includes planarizing a first surface of thefirst substrate to form a planarized topography comprising the firstsurface and a surface of the one or more first embedded conductiveinterconnect structures. At block 1306, the process includes depositinga first embedded layer (such as embedded layer 304, for example) overthe first surface of the first substrate and the one or more firstembedded conductive interconnect structures.

At block 1308, the process includes planarizing the first embedded layeruntil revealing the surface of the one or more first embedded conductiveinterconnect structures and forming a bonding surface of the firstembedded layer, a first recessed portion of the one or more firstembedded conductive interconnect structures at least partially filledwith a portion of the first embedded layer, the portion of the firstembedded layer covering a surface of the first recessed portion of theone or more first embedded conductive interconnect structures.

In an implementation, the process includes suppressing a surfacemobility of atoms of a material of the first recessed portion bycovering the surface of the first recessed portion with the firstembedded layer.

In an implementation, the process includes forming one or more secondembedded conductive interconnect structures in a second substrate;planarizing a first surface of the second substrate to form a planarizedtopography comprising the first surface of the second substrate and asurface of the one or more second embedded conductive interconnectstructures; bonding the first surface of the second substrate to thebonding surface of the first substrate via direct bonding withoutadhesive; and directly bonding the one or more second embeddedconductive interconnect structures to the one or more first embeddedconductive interconnect structures.

In a further implementation, the process includes depositing a secondembedded layer over the first surface of the second substrate and theone or more second embedded conductive interconnect structures; andplanarizing the second embedded layer until revealing the surface of theone or more second embedded conductive interconnect structures andforming a second bonding surface of the second bonding layer, a firstrecessed portion of the one or more second embedded conductiveinterconnect structures at least partially filled with a portion of thesecond embedded layer, the portion of the second embedded layer coveringa surface of the first recessed portion of the one or more secondembedded conductive interconnect structures.

In an implementation, the process further includes bonding the portionof the second embedded layer to the portion of the first embedded layervia direct bonding without adhesive.

As an alternate implementation, the process includes forming one or morefirst embedded conductive interconnect structures in a first substrate;planarizing a first surface of the first substrate to form a planarizedtopography comprising the first surface and a surface of the one or morefirst embedded conductive interconnect structures; selectively removinga portion of the first surface such that the one or more first embeddedconductive interconnect structures protrudes above the first surface ofthe first substrate; depositing a first embedded layer over the firstsurface of the first substrate and the one or more first embeddedconductive interconnect structures, the first embedded layer contactinga portion of a side wall of the one or more first embedded conductiveinterconnect structures; and planarizing the first embedded layer untilrevealing the surface of the one or more first embedded conductiveinterconnect structures and forming a bonding surface of the firstembedded layer and the surface of the one or more first embeddedconductive interconnect structures.

FIG. 14 illustrates a representative process 1400 of forming openings(such as openings 702, for example) in the surface of conductiveinterconnect structures (such as conductive interconnect structures 114,for example) at the bonding surface of a die (such as die 302, forexample), wafer, or other substrate of interest, according to variousembodiments. For instance, the openings may be formed in the conductiveinterconnect structures. The process 1400 refers to FIGS. 7A-12.

In an implementation, at block 1402, the process 1400 includes formingone or more first cavities in a first surface of a first substrate.

At block 1404, the process includes forming one or more first embeddedconductive interconnect structures within the one or more firstcavities, including forming one or more of the first embedded conductiveinterconnect structures to have a first recessed portion in an exposedsurface of the one or more first embedded conductive interconnectstructures.

In an implementation, the process includes forming the one or more firstembedded conductive interconnect structures and the first recessedportion by partially filling the one or more first cavities using adamascene process. In an embodiment, the one or more first embeddedconductive interconnect structures comprise a conformal metal coatingover one or more interior surfaces of the one or more first cavities.

In an implementation, the process includes depositing a protective layerover the first recessed portion of the one or more first embeddedconductive interconnect structures. In a further implementation, theprocess includes depositing one or more additional layers over theprotective layer, at least one of the one or more additional layersincluding a dielectric material.

At block 1406, the process includes planarizing the first surface of thefirst substrate to form a first planarized bonding surface comprisingthe first surface and the exposed surface of the one or more firstembedded conductive interconnect structures

In an implementation, the process includes forming one or more secondembedded conductive interconnect structures in a second substrate,including forming one or more of the second embedded conductiveinterconnect structures to have a second recessed portion in an exposedsurface of the one or more second embedded conductive interconnectstructures; planarizing a first surface of the second substrate to forma second planarized bonding surface comprising the first surface of thesecond substrate and the exposed surface of the one or more secondembedded conductive interconnect structures; bonding the secondplanarized bonding surface of the second substrate to the firstplanarized bonding surface of the first substrate via direct bondingwithout adhesive; and directly bonding the one or more second embeddedconductive interconnect structures to the one or more first embeddedconductive interconnect structures.

In a further implementation, the process includes depositing aprotective layer over the second recessed portion of the one or moresecond embedded conductive interconnect structures. In an example theprocess includes suppressing a surface mobility of atoms of a materialof the second recessed portion by covering the surface of the secondrecessed portion with the protective layer. In another example theprocess includes controlling a direction of expansion of the material ofthe one or more second embedded conductive interconnect structures bycovering the surface of the second recessed portion with the protectivelayer.

As an alternate implementation, the process includes forming one or morefirst cavities in a first surface of a first substrate; forming one ormore first embedded conductive interconnect structures with one or moreopenings within the one or more first cavities; and forming a planarsurface comprising one or more of the first embedded conductiveinterconnect structures having one or more openings.

As another alternate implementation, the process includes forming one ormore first cavities in a first surface of a first substrate; forming oneor more first embedded conductive interconnect structures with one ormore openings within the one or more first cavities; forming a planarsurface comprising one or more of the first embedded conductiveinterconnect structures having one or more openings; and directlybonding the planar surface of the interconnect structures with openingsto the prepared surface of a second substrate.

In various embodiments, some process steps may be modified oreliminated, in comparison to the process steps described herein.

The techniques, components, and devices described herein are not limitedto the illustrations of FIGS. 1A-15, and may be applied to otherdesigns, types, arrangements, and constructions including with otherelectrical components without departing from the scope of thedisclosure. In some cases, additional or alternative components,techniques, sequences, or processes may be used to implement thetechniques described herein. Further, the components and/or techniquesmay be arranged and/or combined in various combinations, while resultingin similar or approximately identical results.

CONCLUSION

Although the implementations of the disclosure have been described inlanguage specific to structural features and/or methodological acts, itis to be understood that the implementations are not necessarily limitedto the specific features or acts described. Rather, the specificfeatures and acts are disclosed as representative forms of implementingexample devices and techniques.

What is claimed is:
 1. A microelectronic assembly, comprising: a firstsubstrate having a bonding surface, the bonding surface of the firstsubstrate having a planarized topography; first and second conductiveinterconnect structures embedded in the first substrate and exposed atthe bonding surface of the first substrate, the second conductiveinterconnect structure having a larger surface area at the bondingsurface than the first conductive interconnect structure; a firstrecessed portion disposed in a surface of the first conductiveinterconnect structure; and a second recessed portion disposed in asurface of the second conductive interconnect structure, the secondrecessed portion having a larger volume than the first recessed portion,the first and second recessed portions at least partially filled with afirst embedded layer.
 2. The microelectronic assembly of claim 1,further comprising a second substrate having a bonding surface, thebonding surface of the second substrate having a planarized topographyand directly bonded to the bonding surface of the first substratewithout an adhesive; and first and second conductive interconnectstructures embedded in the second substrate and exposed at the bondingsurface of the second substrate, the second conductive interconnectstructure of the second substrate having a larger surface area at thebonding surface than the first conductive interconnect structure of thesecond substrate, the first conductive interconnect structure of thesecond substrate directly bonded to the first conductive interconnectstructure of the first substrate and the second conductive interconnectstructure of the second substrate directly bonded to the secondconductive interconnect structure of the first substrate.
 3. Themicroelectronic assembly of claim 2, further comprising a first recessedportion disposed in a surface of the first conductive interconnectstructure of the second substrate and a second recessed portion disposedin a surface of the second conductive interconnect structure of thesecond substrate, the first and second recessed portions of the secondsubstrate at least partially filled with a second embedded layer, thesecond embedded layer directly bonded to the first embedded layerwithout adhesive.
 4. The microelectronic assembly of claim 3, whereinthe first conductive interconnect structures of the first and secondsubstrates form a first conductive interconnect and the secondconductive interconnect structures of the first and second substratesform a second conductive interconnect, and wherein the first recessedportions of the first and second substrates form a first cavity withinthe first conductive interconnect and the second recessed portions ofthe first and second substrates form a second cavity within the secondconductive interconnect, the first and second cavities fully lined withthe second embedded layer and the first embedded layer.
 5. Themicroelectronic assembly of claim 4, wherein the second cavity has avolume that is greater than a volume of the first cavity.
 6. Themicroelectronic assembly of claim 1, further comprising one or morecavities in the surface of the first and/or second conductiveinterconnect structures of the first substrate, within a perimeter ofthe first and/or second conductive interconnect structures of the firstsubstrate, the one or more cavities filled with the first embeddedlayer.
 7. The microelectronic assembly of claim 2, wherein the secondconductive interconnect structures of the first and second substrateshave a surface width dimension greater than 5 microns.
 8. Themicroelectronic assembly of claim 1, wherein the first embedded layer iscomprised of a silicon-containing material.
 9. The microelectronicassembly of claim 8, wherein the silicon-containing material comprisesSiC, SiC/SiO₂, SiN/SiO₂, or a silicide.
 10. The microelectronic assemblyof claim 1, wherein the conductive material of the first embedded layeris different from a material of the first and second conductiveinterconnect structures.
 11. The microelectronic assembly of claim 1,wherein a melting point or coefficient of thermal expansion (CTE) of amaterial of the first embedded layer is greater than a melting point orCTE of a material of the first conductive interconnect structure.
 12. Amicroelectronic assembly, comprising: a first substrate having a bondingsurface, the bonding surface of the first substrate having a planarizedtopography, a first conductive interconnect structure embedded in thefirst substrate with a first embedded layer on a portion of the surfaceof the first conductive interconnect structure; a second substratehaving a bonding surface, the bonding surface of the second substratehaving a planarized topography, a second conductive interconnectstructure embedded in the second substrate with a second embedded layeron a portion of the surface of the second conductive interconnectstructure; a bond interface at which the bonding surface of the firstsubstrate is bonded to the bonding surface of the second substrate, thefirst and second embedded layers of the first and second substratescontacting and forming an enclosed cavity.
 13. The microelectronicassembly of claim 12, wherein the first and second embedded layers areconformal to the first and second conductive interconnect structures,respectively.
 14. The microelectronic assembly of claim 12, wherein thecavity extends more than 100 nm below the bond interface.
 15. Amicroelectronic assembly, comprising: a first substrate having a bondingsurface, the bonding surface of the first substrate having a planarizedtopography; one or more first conductive interconnect structuresembedded in the first substrate and exposed at the bonding surface ofthe first substrate; and a first recessed portion disposed in a surfaceof at least one of the one or more first conductive interconnectstructures, wherein a depth of the first recessed portion is larger than20 nm.
 16. The microelectronic assembly of claim 15, further comprisinga second substrate having a bonding surface, the bonding surface of thesecond substrate having a planarized topography and directly bonded tothe bonding surface of the first substrate without an adhesive; and oneor more second conductive interconnect structures embedded in the secondsubstrate and exposed at the bonding surface of the second substrate,the one or more second conductive interconnect structures directlybonded to the one or more first conductive interconnect structures. 17.The microelectronic assembly of claim 16, further comprising a secondrecessed portion disposed in a surface of at least one of the one ormore second conductive interconnect structures, a volume of the secondrecessed portion corresponding to an expansion of the material of theone or more second conductive interconnect structures when heated to thepredetermined temperature.
 18. The microelectronic assembly of claim 17,wherein the one or more second conductive interconnect structures andthe one or more first conductive interconnect structures form one ormore conductive interconnects, and wherein the first recessed portionand the second recessed portion form a cavity within at least one of theone or more conductive interconnects,
 19. The microelectronic assemblyof claim 18, wherein the cavity is partly or fully lined with aprotective layer.
 20. The microelectronic assembly of claim 19, whereinthe protective layer contains silicon.
 21. The microelectronic assemblyof claim 20, wherein the protective layer is comprised of SiC, SiC/SiO₂,or SiN/SiO₂.
 22. The microelectronic assembly of claim 19, wherein theprotective layer is comprised of tungsten, an alloy of tungsten, nickel,a nickel alloy, cobalt, an alloy of cobalt, tantalum, an alloy oftantalum, titanium, or an alloy of titanium.
 23. The microelectronicassembly of claim 19, further comprising a dielectric layer disposedover the protective layer.
 24. The microelectronic assembly of claim 15,wherein the first recessed portion is disposed within a perimeter of theone or more first conductive interconnect structures.
 25. Themicroelectronic assembly of claim 15, wherein the one or more firstconductive interconnect structures comprise multiple conductiveinterconnect structures with different widths and/or surface areas atthe bonding surface.
 26. The microelectronic assembly of claim 21,wherein the one or more first conductive interconnect structures has asurface width dimension greater than 10 microns.